[PATCH 5/5] d3dcompiler: Allocate temporary registers for variables.
Zebediah Figura
z.figura12 at gmail.com
Sun Mar 29 21:53:20 CDT 2020
From: Zebediah Figura <zfigura at codeweavers.com>
Signed-off-by: Zebediah Figura <zfigura at codeweavers.com>
---
dlls/d3dcompiler_43/d3dcompiler_private.h | 11 +-
dlls/d3dcompiler_43/hlsl.y | 172 ++++++++++++++++++++++
dlls/d3dcompiler_43/utils.c | 2 +-
3 files changed, 183 insertions(+), 2 deletions(-)
diff --git a/dlls/d3dcompiler_43/d3dcompiler_private.h b/dlls/d3dcompiler_43/d3dcompiler_private.h
index 4fdb464a4ef..784a1ae1136 100644
--- a/dlls/d3dcompiler_43/d3dcompiler_private.h
+++ b/dlls/d3dcompiler_43/d3dcompiler_private.h
@@ -150,7 +150,7 @@ static inline void *d3dcompiler_realloc(void *ptr, SIZE_T size)
{
if (!ptr)
return d3dcompiler_alloc(size);
- return HeapReAlloc(GetProcessHeap(), 0, ptr, size);
+ return HeapReAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, ptr, size);
}
static inline BOOL d3dcompiler_free(void *ptr)
@@ -643,6 +643,13 @@ struct source_location
unsigned int col;
};
+struct hlsl_reg
+{
+ unsigned int reg;
+ unsigned char writemask;
+ unsigned char allocated;
+};
+
enum hlsl_ir_node_type
{
HLSL_IR_ASSIGNMENT = 0,
@@ -708,6 +715,7 @@ struct hlsl_ir_var
struct list scope_entry, param_entry;
unsigned int first_write, last_read;
+ struct hlsl_reg reg;
};
struct hlsl_ir_function
@@ -1113,6 +1121,7 @@ const char *debug_base_type(const struct hlsl_type *type) DECLSPEC_HIDDEN;
const char *debug_hlsl_type(const struct hlsl_type *type) DECLSPEC_HIDDEN;
const char *debug_modifiers(DWORD modifiers) DECLSPEC_HIDDEN;
const char *debug_node_type(enum hlsl_ir_node_type type) DECLSPEC_HIDDEN;
+const char *debug_writemask(DWORD writemask) DECLSPEC_HIDDEN;
void debug_dump_ir_function_decl(const struct hlsl_ir_function_decl *func) DECLSPEC_HIDDEN;
void free_hlsl_type(struct hlsl_type *type) DECLSPEC_HIDDEN;
diff --git a/dlls/d3dcompiler_43/hlsl.y b/dlls/d3dcompiler_43/hlsl.y
index d6c64edcace..f828e05e335 100644
--- a/dlls/d3dcompiler_43/hlsl.y
+++ b/dlls/d3dcompiler_43/hlsl.y
@@ -2732,6 +2732,177 @@ static void compute_liveness(struct hlsl_ir_function_decl *entry_func)
compute_liveness_recurse(entry_func->body, 0, 0);
}
+struct liveness_ctx
+{
+ size_t count;
+ struct
+ {
+ /* 0 if not live yet. */
+ unsigned int last_read;
+ } *regs;
+};
+
+static unsigned char get_dead_writemask(struct liveness_ctx *liveness,
+ unsigned int first_write, unsigned int index, unsigned int components)
+{
+ unsigned char i, writemask = 0, count = 0;
+
+ for (i = 0; i < 4; ++i)
+ {
+ if (liveness->regs[index + i].last_read <= first_write)
+ {
+ writemask |= 1 << i;
+ if (++count == components)
+ return writemask;
+ }
+ }
+
+ return 0;
+}
+
+static struct hlsl_reg allocate_temp_register(struct liveness_ctx *liveness,
+ unsigned int first_write, unsigned int last_read, unsigned char components)
+{
+ struct hlsl_reg ret = {.allocated = TRUE};
+ unsigned char writemask, i;
+ unsigned int regnum;
+
+ for (regnum = 0; regnum < liveness->count; regnum += 4)
+ {
+ if ((writemask = get_dead_writemask(liveness, first_write, regnum, components)))
+ break;
+ }
+ if (regnum == liveness->count)
+ {
+ liveness->count = max(liveness->count * 2, 32);
+ liveness->regs = d3dcompiler_realloc(liveness->regs, liveness->count * sizeof(*liveness->regs));
+ writemask = (1 << components) - 1;
+ }
+ for (i = 0; i < 4; ++i)
+ {
+ if (writemask & (1 << i))
+ liveness->regs[regnum + i].last_read = last_read;
+ }
+ ret.reg = regnum / 4;
+ ret.writemask = writemask;
+ return ret;
+}
+
+static BOOL is_range_dead(struct liveness_ctx *liveness, unsigned int first_write,
+ unsigned int index, unsigned int elements)
+{
+ unsigned int i;
+
+ for (i = 0; i < elements; i += 4)
+ {
+ if (!get_dead_writemask(liveness, first_write, index + i, 4))
+ return FALSE;
+ }
+ return TRUE;
+}
+
+/* "elements" is the total number of consecutive whole registers needed. */
+static struct hlsl_reg allocate_temp_range(struct liveness_ctx *liveness,
+ unsigned int first_write, unsigned int last_read, unsigned int elements)
+{
+ struct hlsl_reg ret = {.allocated = TRUE};
+ unsigned int i, regnum;
+
+ elements *= 4;
+
+ for (regnum = 0; regnum < liveness->count; regnum += 4)
+ {
+ if (is_range_dead(liveness, first_write, regnum, min(elements, liveness->count - regnum)))
+ break;
+ }
+ if (regnum + elements >= liveness->count)
+ {
+ liveness->count = max(liveness->count * 2, regnum + elements);
+ liveness->regs = d3dcompiler_realloc(liveness->regs, liveness->count * sizeof(*liveness->regs));
+ }
+ for (i = 0; i < elements; ++i)
+ liveness->regs[regnum + i].last_read = last_read;
+ ret.reg = regnum / 4;
+ return ret;
+}
+
+static void allocate_variable_temp_register(struct hlsl_ir_var *var, struct liveness_ctx *liveness)
+{
+ if (!var->reg.allocated && var->last_read)
+ {
+ if (var->data_type->reg_size > 1)
+ {
+ var->reg = allocate_temp_range(liveness, var->first_write,
+ var->last_read, var->data_type->reg_size);
+ TRACE("Allocated r%u-r%u to %s (liveness %u-%u).\n", var->reg.reg,
+ var->reg.reg + var->data_type->reg_size - 1, var->name, var->first_write, var->last_read);
+ }
+ else
+ {
+ var->reg = allocate_temp_register(liveness, var->first_write,
+ var->last_read, var->data_type->dimx);
+ TRACE("Allocated r%u%s to %s (liveness %u-%u).\n", var->reg.reg,
+ debug_writemask(var->reg.writemask), var->name, var->first_write, var->last_read);
+ }
+ }
+}
+
+static void allocate_temp_registers_recurse(struct list *instrs, struct liveness_ctx *liveness)
+{
+ struct hlsl_ir_node *instr;
+
+ LIST_FOR_EACH_ENTRY(instr, instrs, struct hlsl_ir_node, entry)
+ {
+ switch (instr->type)
+ {
+ case HLSL_IR_ASSIGNMENT:
+ {
+ struct hlsl_ir_assignment *assignment = assignment_from_node(instr);
+ allocate_variable_temp_register(hlsl_var_from_deref(&assignment->lhs), liveness);
+ break;
+ }
+ case HLSL_IR_IF:
+ {
+ struct hlsl_ir_if *iff = if_from_node(instr);
+ allocate_temp_registers_recurse(iff->then_instrs, liveness);
+ if (iff->else_instrs)
+ allocate_temp_registers_recurse(iff->else_instrs, liveness);
+ break;
+ }
+ case HLSL_IR_LOOP:
+ {
+ struct hlsl_ir_loop *loop = loop_from_node(instr);
+ allocate_temp_registers_recurse(loop->body, liveness);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+}
+
+/* Simple greedy temporary register allocation pass that just assigns a unique
+ * index to all (simultaneously live) variables or intermediate values. Agnostic
+ * as to how many registers are actually available for the current backend, and
+ * does not handle constants. */
+static void allocate_temp_registers(struct hlsl_ir_function_decl *entry_func)
+{
+ struct liveness_ctx liveness = {};
+ struct hlsl_ir_var *var;
+
+ LIST_FOR_EACH_ENTRY(var, &hlsl_ctx.globals->vars, struct hlsl_ir_var, scope_entry)
+ {
+ allocate_variable_temp_register(var, &liveness);
+ }
+
+ LIST_FOR_EACH_ENTRY(var, entry_func->parameters, struct hlsl_ir_var, param_entry)
+ {
+ allocate_variable_temp_register(var, &liveness);
+ }
+
+ allocate_temp_registers_recurse(entry_func->body, &liveness);
+}
+
struct bwriter_shader *parse_hlsl(enum shader_type type, DWORD major, DWORD minor,
const char *entrypoint, char **messages)
{
@@ -2798,6 +2969,7 @@ struct bwriter_shader *parse_hlsl(enum shader_type type, DWORD major, DWORD mino
}
compute_liveness(entry_func);
+ allocate_temp_registers(entry_func);
out:
TRACE("Freeing functions IR.\n");
diff --git a/dlls/d3dcompiler_43/utils.c b/dlls/d3dcompiler_43/utils.c
index 94f7ee59e75..af625d6ac6f 100644
--- a/dlls/d3dcompiler_43/utils.c
+++ b/dlls/d3dcompiler_43/utils.c
@@ -2069,7 +2069,7 @@ static void debug_dump_ir_constructor(const struct hlsl_ir_constructor *construc
wine_dbg_printf(")");
}
-static const char *debug_writemask(DWORD writemask)
+const char *debug_writemask(DWORD writemask)
{
static const char components[] = {'x', 'y', 'z', 'w'};
char string[5];
--
2.25.1
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